1. Field of the Invention
The present invention relates to the placement of line traces on printed circuit substrates such that the number of power pins for an integrated circuit can be minimized and/or the impedance of the traces is controlled to thereby provide an environment for high speed signal transmission.
1. Description of the Related Art
The level change rate of a digital signal is commonly called the speed or the frequency of the signal. In digital circuits, a signal path constitutes several physical segments, e.g., the bond wire within an integrated circuit "IC", the IC pin, the printed circuit board "PCB" traces between vias, the via themselves, the connector pins, the PCB edge connector finger, etc. Each of these line segments has associated parasitics such as resistance, inductance and capacitance. The impedance of a line is a function of these parasitics. When there is an impedance mismatch between two of these segments, a discontinuity occurs and a signal reflection will occur at the discontinuity. Depending on the nature of the impedance mismatch, the reflected signal phase and amplitude will be "added" or "subtracted" from the original signal. The result affects the shape of the original signal at different locations of the signal path. The reflection can travel back-and-forth several times between two mismatched points on the line until the total reflected signal amplitude is diminished by the reflective signal amplitude cancellation and the resistive loss in the trace.
In short, an impedance mismatch can detrimentally effect the shape of a signal traveling on a line (rising-edge, falling-edge, and steady state) enough to cause a misinterpretation of the signal by the receiving electronics. The higher the signal speed the more critical impedance matching becomes.
A PCB or a connector is said to be impedance controlled when the characteristic impedance (Z.sub.0) of its signal traces are designed to all have an impedance within a predefined tolerance. Ideally, a manufacturer would like to design traces on a PCB at a minimal cost without sacrificing necessary performance.
In a multi layer PCB (where there are more than two (2) conductive, etched layers), power planes are usually implemented to separate "signal planes". This design enables the characteristic impedance (Z.sub.0) of the traces on the signal planes to be controlled with relative ease. The impedance control is related to placing the power or ground planes a predetermined distance from the signal planes thereby establishing a relatively constant capacitance. Furthermore, for a given multi layer PCB having a dielectric constant, metal signal traces (typically copper), and a given board thickness, the characteristic impedance (Z.sub.0) of a trace is directly proportional to the distance (h) a trace is from a power/ground plane, and it is inversely proportional to the width (w) of a trace in accordance with the relationships:
Z.sub.0 .alpha. (h, 1/w) PA1 Z.sub.0 .alpha. (h, 1/w)
On the other hand, if the PCB is a two layer board (having only two (2) etched, conductive layers), then controlling the characteristic impedance (Z.sub.0) becomes difficult. On a two layer board the characteristic impedance (Z.sub.0) of a trace is directly proportional to the distance (h) and spacing (s) of the trace to a power or ground on the other side of the two layer PCB, it is inversely proportional to the width (w) of a trace. This calculation becomes very complex as traces are opposite to and are cris-crossed by power, ground and signal traces on the other side of the two (2) layer board. In general the most simple relationship is:
In the semiconductor industry, technology is pushing electronics to become smaller and smaller in size. More, and more circuitry is being placed into a single integrated circuit. Sometimes circuits are split onto two separate pieces of silicon that must be interconnected when installed on a PCB. The communication between the two circuits is generally at a very high rate of speed (in the hundreds to thousands of megahertz range) and the characteristic impedance (Z.sub.0) of the traces between the circuits becomes very important so that signal reflections do not inhibit transmission.
On two layer PCB boards, large power planes are not normally incorporated because the board thickness is generally too thick for a power plane to be effective and because the power planes use up too much space on the PCB. Instead, a technique of interleaving might be used. FIG. 1 depicts a common technique used to provide some control over the characteristic impedance of traces on a two layer PCB. Generally, power or ground traces are interleaved with the signal traces on a single side of the PCB and only control a degree of crosstalk.
The problem when controlling the impedance of signal traces is providing enough power or ground traces from an integrated circuit or other source to interleave between a plurality of high speed signal lines.
In summary, there is a need for a low cost technique for controlling the characteristic impedance (Z.sub.0) of signal traces on a two layer PCB. Furthermore, there is a need for a technique to control the characteristic impedance (Z.sub.0) of line traces without requiring a large number of power or ground pins on integrated circuits to provide power or ground traces to interleave between signal traces.